----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:31:49 09/25/2013 
-- Design Name: 
-- Module Name:    carry_save_adder - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity carry_save_adder is
	port(	a : in STD_LOGIC_VECTOR(63 downto 0);
			b : in STD_LOGIC_VECTOR(63 downto 0);
			c : in STD_LOGIC_VECTOR(63 downto 0);
			carry : out STD_LOGIC_VECTOR(63 downto 0);
			partialSum : out STD_LOGIC_VECTOR(63 downto 0));
end carry_save_adder;

architecture Behavioral of carry_save_adder is
	signal carryIntermediate : STD_LOGIC_VECTOR(63 downto 0) := X"0000000000000000";
begin
	partialSum <= (a xor b) xor c;
	carryIntermediate <= (a and b) or (a and c) or (b and c);
	carry <= carryIntermediate(62 downto 0) & '0';
end Behavioral;

